High-Level Synthesis for Reliable and Energy-Efficient ASICs

Ever increasing performance demand from computer applications has resulted in shrinking technology sizes of CMOS circuits every 18 months over the past 40 years. Shrinking technology sizes made it possible to increase the number of transistors on chips. As a result, designers are able to embed more components on a single chip than ever. While smaller transistor sizes reduce the cost of chips as a result of having smaller chip area, the increase in circuit densities makes the design process more challenging than before. Each technology generation also introduces new design problems in digital systems. For example, when the technology sizes are reduced, the circuits become more vulnerable to radiation effects; thus, the transient faults increase in the circuits. While the error correcting codes (i.e., Hamming codes) can be used to reduce the effects of transient errors for memory elements; for combinational circuits, double or triple redundancy-based methods are used to determine the errors. However, redundancy-based error detection methods increase the chip area and the cost.

While the reduced technology size makes the circuits more susceptible to transient faults, some energy reduction techniques also negatively affects their reliabilities. For example, when dynamic voltage scaling (DVS) is applied as an energy reduction method, the circuit consumes less energy under lower voltage levels; however, lowering the supply voltage also reduces the reliability of the circuit. When we consider the design of an application with large number of components, tackling all system requirements such as area, performance, energy consumption and reliability may need new systematic design methods. Thus, the design process of application specific integrated circuits (ASICs) must consider all these requirements on higher level of abstraction. High level synthesis (HLS) process aims to integrate all system requirements on higher level of abstraction and remedy the designer from lower level design burdens.

Traditional HLS methods usually consider only area, performance, and energy optimizations and most of the previous work ignore the overall system reliability. Especially, the effect of DVS on reliability is completely ignored by the previous studies when they aim to minimize energy consumption by using DVS. In this work, we aim to develop new HLS methods for ASIC design under area and performance constraints and with low energy consumption and high reliability.