Reconfigurable Network-on-Chips

Network-on-Chip (NoC) is a communication infrastructure for chips consisting too many processing elements. It has been created as a better alternative to classical bus-based communication method and it inherits most of the computer network concepts. When a NoC architecture is designed, the designer should consider performance, cost, fault-tolerance and energy consumption criteria as the chips have limited resources on them. The NoC topology plays an important role to meet the aforementioned criteria of the final network design. For example, a regular topology (such as mesh) might be preferable due to its scalability, fault-tolerance, and reusability for different applications whereas an irregular topology can be favorable due to its huge optimization space for performance, energy, and cost. If we can merge the benefits of these two different topology types, we can have higher chances to meet the required criteria for the applications.

Motivated by this observation, in this project, we aim to add reconfigurability to both mesh-based and irregular topology-based NoC designs. We can list the topics and goals of this project as follows:

Reconfigurable mesh topology design: We plan to add configurable units between the routers of the mesh topology to make it reconfigurable. By changing the unit configuration, we will be able to imitate the mesh topology to be an irregular topology and dynamically change the routing path of a packet in case of network congestion. This will allow us 1) to shut down unused routers to save static energy and 2) to send less data on network resources to save dynamic energy. Making mesh topology fault-tolerant: We can tolerate permanent faults as well as transient faults by using reconfiguration capability of meshes. We will design a fault detection mechanism by using parity bits. This unit will detect the fault, its location and type. Using this information, our control mechanism will reroute packets on healthy paths by reconfiguring the configuration units. Developing adaptive routing algorithm: We will design an adaptive routing algorithm that dynamically changes the routing paths of the packets by using traffic distribution, faulty path information, and deadlock and livelock conditions of the packets. Reconfigurable application-specific topology design: In our previous Tubitak 1001 project, we proposed a method that generates fault tolerant irregular topologies under one permanent link failure. However, in this method, faults must be detected under test during fabrication and can cover only a single link fault. In our current project proposal, we aim to add fault detection mechanism on routers that can detect the multiple faults dynamically when application is running. This fault detection and control unit on a router will also update the routing information of a packet if there is a fault on its path. Studying the 3D adaptation of proposed methods: We will investigate the adaptation possibilities of mesh and irregular topology reconfiguration methods and adaptive routing algorithm for 3D NoCs.